The present invention relates to a method for fabricating a semiconductor device having a capacitor.
A semiconductor device having a capacitor which uses a ferroelectric film or a high dielectric film as a capacitor insulating film has a remanent polarization resulting from a hysteresis characteristic or a high specific dielectric constant. In the field of a nonvolatile memory and a DRAM, therefore, a possibility is that a capacitor using a ferroelectric film or a high dielectric film as a capacitor insulating film will be used widely as a replacement for a capacitor having a capacitor insulating film composed of a silicon oxide film or a silicon nitride film. In this case, a capacitor is requested to have a three-dimensional configuration for a further reduction in the area of a memory cell.
A conventional method for fabricating a semiconductor device will be described herein below with reference to FIGS. 16A to 16C and FIGS. 17A to 17C.
First, as shown in FIG. 16A, a first silicon oxide film 11 is formed by CVD on a semiconductor substrate 10 and then planarized by CMP. Then, selective dry etching is performed with respect to the first silicon oxide film 11 to form a contact hole for exposing the semiconductor substrate 10. Subsequently, a titanium film and a titanium nitride film are formed by sputtering or CVD in such a manner as to fill in the contact hole and a tungsten film is further formed by CVD.
Next, a metal film composed of the titanium film, the titanium nitride film, and the tungsten film is left only in the contact hole by CMP to form a plug 12. Then, a multilayer film composed of a titanium-aluminum nitride film, an iridium film, and an iridium oxide film which are stacked successively in layers are formed by sputtering over the first silicon oxide film 11 and the plug 12. Subsequently, selective dry etching is performed with respect to the multilayer film, thereby forming an oxygen barrier film 13 covering the plug 12.
Next, as shown in FIG. 16B, a second silicon oxide film 14 is formed over the first silicon oxide film 11 in such a manner as to cover the oxygen barrier film 13 and then planarized by CMP. Then, as shown in FIG. 16C, a resist mask 15 having an opening pattern 15a above the oxygen barrier layer 13 is formed on the second silicon oxide film 14.
Next, as shown in FIG. 17A, etching is performed with respect to the second silicon oxide film 14 by using the resist mask 15 having the opening pattern 15a, thereby forming an opening 14a for exposing the oxygen barrier film 13. In this case, the oxygen barrier film 13 is over etched and the film thickness of the resist mask 15 is reduced by etching.
Next, as shown in FIG. 17B, the remaining resist mask 15 is removed by ashing. Then, as shown in FIG. 17C, a first platinum film is formed by sputtering over the second silicon oxide film 14 and in the opening 14a. Subsequently, selective dry etching is performed with respect to the first platinum film in a region including the opening 14a, thereby forming a lower electrode 16 composed of the patterned first platinum film. Then, a ferroelectric film composed of a bismuth layer-structured Perovskite-type oxide, the components of which are strontium, bismuth, tantalum, and niobium, is formed by MOCVD over the second silicon oxide film 14 and the lower electrode 16. After a second platinum film is then formed by sputtering on the ferroelectric film, the ferroelectric film and the second platinum film are patterned in a region including the lower electrode 16, whereby a capacitor insulating film 17 and an upper electrode 18 are formed. Thereafter, wiring, a protective film, and the like are formed, though they are not disclosed.
In accordance with the foregoing fabrication method, however, the coverage of the lower electrode 16, the capacitor insulating film 17, and the upper electrode 18 composing a capacitor is insufficient so that the cross section of the capacitor is likely to have an overhung configuration. Consequently, a broken wire may occur in the lower electrode 16 or in the upper electrode 18. In addition, the film thickness of the capacitor becomes smaller with approach toward the bottom portion of the wall surface of the opening 14a, while the film thickness of the capacitor is also reduced at the bottom portion of the opening 14a. Since the coverage is insufficient, variations occur in the characteristics of the capacitor if the thickness of the capacitor insulating film 17 becomes nonuniform.
There are cases where the lower electrode, the capacitor insulating film, and the upper electrode, which are formed when the opening has a vertical configuration in accordance with another conventional method for fabricating a semiconductor device, are not shown in such an inferior coverage condition as shown in FIG. 17C. If sputtering which allows simple and convenient film formation for the upper electrode, the lower electrode, or the capacitor insulating film is used, however, coverage deteriorates in the opening in an actual situation (see, e.g., U.S. Pat. No. 6,239,461, column 5 line 44 to column 6 line 26, FIG. 5). Even if MOCVD (Metal Organic CVD) which relatively improves the coverage is used, coverage is insufficient in practice and the new problem of a lower film-forming rate is encountered if the coverage is to be improved by using the method.
To improve the coverage of the electrodes and the capacitor insulating film, a method of forming the wall surface of the opening into a downwardly tapered configuration when viewed from above (it is assumed hereinafter that, if any mention is made of the configuration of the wall surface in the following description, it refers to a configuration viewed from above). To form an extremely small opening in a silicon oxide film used typically as an interlayer insulating film, it is necessary to form the opening by dry etching. However, reactive etching cannot be performed with respect to a silicon oxide film so that it is difficult to form the wall surface of the opening into a downwardly tapered configuration.
As a method for forming the wall surface of an opening into a downwardly tapered configuration, there has been proposed a method which retracts a resist mask after forming an opening and performs etching again to form the wall surface of the opening into a downwardly tapered configuration (see, e.g., Japanese Laid-Open Patent Publication No. SHO 61-296722, pp. 2 to 3, FIG. 1). In this case, however, an underlying conductive film removed by etching for forming the opening is adhered again to the sidewall of the resist mask used for etching or a reaction product between an etching gas and the conductive film is deposited. The re-adhered conductive film and the reaction product remaining unremoved even after the retraction of the resist mask causes configurational abnormality such as the formation of a fence. In the case of performing etching again, therefore, the configurational abnormality hinders stable formation of the tapered configuration of the wall surface of the opening.
Thus, in accordance with the conventional method for fabricating a semiconductor device, the coverage of the electrodes and the capacitor insulating film is insufficient and the cross sections thereof are likely to present overhung configurations. If the coverage of the electrodes deteriorates, a broken wire occurs in the electrode. If the electrodes present overhung configurations, the width of the space in the upper portion of the opening is reduced so that the coverage of the capacitor insulating film is further degraded. This leads to a leakage current flowing in the capacitor insulating film and variations in the characteristics of the capacitor.
In the case of forming the capacitor insulating film by MOCVD (Metal Organic CVD), on the other hand, the raw materials of organic metals are supplied at nonuniform rates so that the composition of the capacitor insulating film becomes nonuniform. In addition, a method for stably forming the tapered configuration of the wall surface of the opening is unknown.